Samsung Unveils 3D Stacked FETs: Triple Nanosheet Channels at 42nm

At the 2026 VLSI Symposium (held June 14–18), the Semiconductor Research Center at Samsung Electronics debuted a groundbreaking paper titled “First Demonstration of 3D Stacked FETs at Gate Pitch of 42 nm Featuring Triple Stacked Nanosheet Channels for Advanced Logic Applications.”

Research Accolades This submission was recognized as a Best Paper, achieving an impressive evaluation score of $\text{8.29/10}$. Out of more than 1,000 entries, it was selected as a 2026 VLSI Technical Highlight and included in the official Press Kit for global media.

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1. The Evolutionary Path of the Transistor

To understand the leap to 3D Stacked FETs, one must look at the history of transistor architecture. The goal has always been the same: increasing the precision of electrical current control.

The Progression Timeline

The industry has moved through several distinct phases:

1. Planar FET: The traditional flat structure.
2. FinFET: Introducing a 3D "fin" to increase surface area.
3. GAA (Gate-All-Around): The gate surrounds the channel entirely for maximum control.
4. 3D Stacked FET: The latest frontier, moving the entire device arrangement into the third dimension.

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2. Breaking the "Planar" Ceiling

In standard logic circuits, n-type and p-type transistors are positioned side-by-side on a flat surface. While this served the industry for decades, we have reached a point of diminishing returns.

The Urban Planning Analogy

Imagine a city where land is running out:

• Phase 1: Build houses closer together.
• Phase 2: Optimize road layouts and open spaces.
• Phase 3: Build skyscrapers.

By utilizing vertical space, cities can house more people on the same plot of land. Similarly, 3D Stacked FETs move the n-type and p-type transistors from a horizontal layout to a vertical stack, drastically increasing transistor density without expanding the chip's footprint.

Feature	Conventional Layout	3D Stacked Layout
Orientation	Horizontal (Side-by-Side)	Vertical (Stacked)
Footprint	Larger $\text{Area}$	Compact $\text{Area}$
Scaling Potential	Limited by 2D plane	High (3D expansion)
Architecture	Planar/FinFET/GAA	Advanced GAA Evolution

The GAA Connection

It is important to note that 3D Stacked FETs are not a departure from GAA technology, but rather its natural evolution. Because GAA uses nanosheet channels that can be layered, it provides the necessary foundation to stack and manage channels vertically.

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3. Overcoming Technical Hurdles

Transitioning to a 3D architecture is not as simple as "stacking blocks." Samsung had to solve three critical engineering problems:

• Current Conduction: Ensuring the device provides enough drive current.
• Crystalline Quality: Creating multiple channel layers that are uniform and high-quality.
• Electrical Isolation: Preventing interference between the upper and lower transistors.

Solution: Triple-Stacked Nanosheet Channels

The "channel" is the primary path for current. If the channel width ($W_{eff}$) is too small, the transistor cannot deliver sufficient current when switched on, which kills performance.

To solve this while maintaining a tiny footprint, Samsung implemented triple-stacked nanosheet channels for both the n-type and p-type transistors.

The Logic: $\text{Effective Width} (W_{eff}) \propto \text{Number of Nanosheets} \times \text{Sheet Width}$

By stacking three sheets vertically, Samsung maintains high current-carrying capability even as the overall device area shrinks.

Quality and Isolation

To ensure the device functions reliably, Samsung focused on the uniformity of the crystal layers.

The final architecture ensures that the top and bottom transistors remain electrically distinct, preventing leakage and ensuring signal integrity.

// Conceptual representation of 3D Stacked FET Logic
struct Transistor {
    string type; // "n-type" or "p-type"
    int nanosheet_count = 3;
    float gate_pitch = 42.0; // nm
};

struct StackedFET {
    Transistor upper; // p-type
    Transistor lower; // n-type
    bool isIsolated = true;
};