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Programmable Probabilistic Computer with 1M p-bits

Original article
arxiv.org|10 points|0 comments|by rbanffy|Jun 28, 2026

Programmable Probabilistic Computer with 1,000,000 p-bits

Reference: arXiv:2606.25313 | Submitted: June 24, 2026 Category: Computer Science > Distributed, Parallel, and Cluster Computing (cs.DC) & Hardware Architecture (cs.AR)


👥 Research Team

The project was spearheaded by a collaborative group including:

  • Navid Anjum Aadit
  • Xiuqi Zhang, Shuvro Chowdhury, Kevin Callahan-Coray, Kyle Lee, Saleh Bunaiyan, Sanjay Seshan, Clayton Thomas, Jason Twigg, Andrew Seawright, Forrest Brewer, Tathagata Srimani, and Kerem Y. Camsari.

🚀 Executive Summary

Historically, probabilistic computers utilizing p-bits (probabilistic bits) have served as specialized hardware accelerators for optimizing Ising models and sampling. However, these systems were restricted to single-chip architectures, which created a hard ceiling on memory bandwidth and total capacity.

This research shatters that limitation by interconnecting multiple FPGAs to form a massive, unified Ising machine. The result is a programmable probabilistic computer boasting one million p-bits.

Key Technical Specifications

FeatureSpecification
Total p-bits1,000,0001,000,0001,000,000
Sampling Rate>1012> 10^{12}>1012 flips per second
Memory StrategyLocal on-chip storage for all coupling weights
Communication1-bit boundary state exchanges

🛠️ System Architecture & Logic

The system operates by partitioning the Ising model across several devices. To maintain efficiency, the devices do not exchange complex data; they only swap the states of the p-bits located at the boundaries of their respective partitions.

Communication Workflow

The Fundamental Question: In a distributed sampler, how often must boundary information be updated to ensure the partitioned system behaves identically to a single, monolithic machine?


🔬 Scientific Findings

The researchers utilized three-dimensional Edwards-Anderson spin glasses to analyze the system's performance. They discovered that the behavior of the machine is governed by a specific timing ratio, denoted as η\etaη:

η=fcommfp−bit\eta = \frac{f_{comm}}{f_{p-bit}}η=fp−bit​fcomm​​

Where:

  • fcommf_{comm}fcomm​ is the frequency of boundary-state exchanges.
  • fp−bitf_{p-bit}fp−bit​ is the local update frequency of the p-bits.

Performance Outcomes

  • High η\etaη (Above Threshold): The distributed system's performance is indistinguishable from a monolithic GPU reference.
  • Low η\etaη (Below Threshold): The system experiences a "throughput-accuracy tradeoff." While the residual energy still follows a power law decay, the exponent is reduced.

This phenomenon was further validated using a cluster mean-field model, proving that this tradeoff is a universal property of partitioned stochastic dynamics.


🎯 Applications & Validation

The platform's versatility was demonstrated through the successful execution of several complex computational tasks:

  • Spin Glasses (3D Edwards-Anderson)
  • Max-Cut problems
  • Boolean Satisfiability (SAT)

Implementation Logic (Pseudocode)

def distributed_gibbs_sampling(p_bits, weights, eta):
    while not converged:
        # Local updates based on on-chip weights
        update_local_pbits(p_bits, weights) 
        
        # Boundary exchange based on timing ratio eta
        if current_cycle % (1/eta) == 0:
            exchange_boundary_bits()
            
        calculate_residual_energy()

📜 Metadata & Licensing

DOI: https://doi.org/10.48550/arXiv:2606.25313 License: license icon

This work was supported by the Simons Foundation and various member institutions.