Intel Commences Shipping High-NA EUV Silicon

Coming soon to a Panther Lake-powered notebook near you!

In April 2024, I had the opportunity to don a bunny suit and enter Intel’s D1X fab in Hillsboro, Oregon. There, I stood beside a machine that is essentially the size of a city bus and carries a price tag comparable to the GDP of a small nation.

Intel Fellow Mark Phillips guided the tour, introducing us to ASML’s inaugural High-NA EUV scanner—a behemoth weighing roughly 165 tons. At the time, installation had just concluded and calibration was underway; it was clear that actual test wafers were still several months away.

Intel's timeline was tightly aligned with ASML's, with the company being only a few weeks ahead in tool installation, fostering a deep technical partnership. During the tour—which included a CNBC crew with approved gear—the primary curiosity was whether this machine would ever move beyond research and into actual production hardware.

The Big Announcement

ASML has now officially confirmed via press release that Intel Foundry has transitioned High-NA EUV into high-volume manufacturing (HVM).

Intel is currently utilizing this technology to pattern specific layers for its latest notebook processors: the Panther Lake (Core Ultra Series 3) chips, which are manufactured on the Intel 18A node.

Key Milestone: Intel and ASML report that these High-NA layers are now "dual-qualified" in Oregon, meaning they yield results equal to those produced by standard EUV tools, despite the latter requiring multiple patterning steps to achieve the same result.

While one might assume these are merely test chips, Intel has confirmed that consumer notebooks containing silicon printed by a $380 million scanner are currently shipping to customers.

Intel Fellow Mark Phillips briefing the group

Understanding the Hardware: What is "High-NA"?

The machine is a staggering architectural feat: two stories of vacuum vessels, stainless piping, and complex cabling surrounding a wafer stage. Everything is designed to optimize a single physical variable: Numerical Aperture (NA).

The Physics of Resolution

In lithography, the Numerical Aperture describes the angle of the light cone gathered by the optics. A wider cone allows for the resolution of finer details.

Standard EUV: $NA = 0.33$
High-NA EUV: $NA = 0.55$

By increasing the NA to $0.55$ , the smallest single-exposure feature is sharpened by approximately one-third.

The Practical Advantage:

Instead of needing two or three separate "Low-NA" exposures that must be perfectly aligned (stitched) together, a fab can print the pattern in a single cycle. This leads to:

Reduced cost per layer
Shorter cycle times
Fewer opportunities for defects

The Trade-offs

Achieving $0.55$ NA isn't free. ASML implemented anamorphic optics (similar to a camera), which magnify the mask differently along the X and Y axes. This results in a significant reduction in the field size the scanner can image in one shot.

Feature	Low-NA EUV	High-NA EUV
Numerical Aperture	$0.33$	$0.55$
Max Field Size	$858\text{ mm}^2$ ( $26 \times 33\text{ mm}$ )	$429\text{ mm}^2$ ( $26 \times 16.5\text{ mm}$ )
Approx. Tool Cost	$\sim \$ 130\text{M} - $190\text{M}$	$\sim \$ 380\text{M}$
Installation Scale	Standard	$\sim 250$ crates / several months

Because the field is halved, a full-reticle die must now be exposed in two halves and stitched together, which partially offsets the simplicity gained by the higher resolution.

ASML's first commercial High-NA EUV system

Strategic Roadmap and Implementation

According to imec's long-term projections, High-NA is a decade-long investment.

Why use it on `18A` now?

The Intel 18A node (roughly equivalent to N2) was originally designed for Low-NA EUV and multi-patterning. It does not require High-NA to function. However, Intel is using it here for a specific strategic reason: Learning.

By "dual-qualifying" layers on both tool types, Intel ensures that if a High-NA wafer fails, the product still ships via Low-NA. This allows their engineers to master the "recipes" now, so that when 14A or 10A arrive—where High-NA becomes a necessity—the process is already seamless.

~~Intel waited too long to adopt EUV during the 10nm era, causing massive delays.~~ This time, Intel is the aggressor, leaving TSMC in the position of the observer.

imec's Long Range roadmap

The Economic Debate

Despite the technical victory, some analysts question the financial logic. SemiAnalysis, citing IBM's research from a 2025 conference, suggests a stark cost difference:

"A single High-NA exposure costs approximately 2.5 times as much as a Low-NA exposure."

This creates a "crossover point" for profitability. The expensive tool only saves money when one High-NA shot replaces three or more Low-NA masks. SemiAnalysis models suggest this economic tipping point for most layers won't occur until roughly 2030.

Summary of Logic

def is_high_na_profitable(num_low_na_masks):
    cost_low_na = 1.0 * num_low_na_masks
    cost_high_na = 2.5 * 1  # Single exposure
    
    if cost_high_na < cost_low_na:
        return "Profitable"
    else:
        return "Too Expensive"

# Example:
print(is_high_na_profitable(2)) # Output: Too Expensive
print(is_high_na_profitable(3)) # Output: Profitable

Final Image