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When Is NVLink Worth It?

Original article
platform-fools.com|17 points|2 comments|by ak_t|Jul 22, 2026

Evaluating the Value of NVLink in 2026

As of April 2026, acquiring NVLink bridges remains a costly endeavor, with prices swinging between 200and200 and 200and400 depending on the specific dimensions and whether you can find a retail bargain.

Given that my rig houses two RTX 3090s, I decided to investigate whether the performance gains for AI workloads actually justify the investment.

🛠️ Experimental Setup

Hardware Specifications

  • CPU: AMD Epyc 7532 (32 Cores, providing 128 PCIe lanes)
  • Motherboard: Supermicro H12SSL-i (featuring 5 PCIe 4.0 x16 slots)
  • Memory: 256GB total (8 Channels of 32GB DDR4-3200)
  • GPUs: 2x EVGA RTX 3090 (positioned in slots 3 and 6, both utilizing full x16\text{x16}x16 bandwidth)
  • Software: Ubuntu 24.04 running Nvidia driver version 595

Testing Methodology

I designed a suite of tests to evaluate different levels of inter-GPU communication requirements:

  • Model Inference (Layer Split): Minimal communication between GPUs.
  • Model Inference (Tensor Parallelism): High communication; requires synchronization at every single layer.
  • Model Training (DDP): Used TinyLlama 1.1B; syncs only once per step to calculate gradients.
  • Model Training (FSDP): Used Qwen2.5 3B; requires continuous, heavy data transfers.

📊 Initial Findings & The "SHM" Trap

Initially, the results seemed straightforward:

  1. Layer Split: No impact.
  2. Tensor Parallelism: Prompt processing speed increased by ≈30%\approx 30\%≈30%, but token generation remained identical. (This was surprising, as I expected frequent activation syncing to benefit from the bridge).
  3. FSDP Training: Showed a massive 3x performance leap. →\rightarrow→ Correction: This data was misleading.

The Technical Pitfall: SHM vs. P2P

In my first round of "non-NVLink" tests, I used the environment variable NCCL_P2P_DISABLE=1. By enabling NCCL_DEBUG=INFO, I discovered a critical detail in the logs:

gpu:11419:11419 [0] NCCL INFO Channel 03 : 0[0] - 1[1] via SHM/direct/direct

This indicated that the system was using Shared Host Memory (SHM). Instead of Peer-to-Peer (P2P) communication over the PCIe bus, the data was taking a round trip through the system RAM, creating a massive bottleneck.

The Catch: You cannot simply disable NVLink via software to force P2P. Setting NCCL_P2P_DISABLE=1 kills both NVLink and PCIe P2P, forcing the slow SHM path.

🔓 Bypassing Nvidia's Restrictions

Even after physically removing the bridge, the system still defaulted to SHM. This is because Nvidia artificially disables P2P on consumer-grade GPUs to segment their product line. However, the hardware is physically capable of it.

To fix this, I utilized the open-gpu-kernel-modules patch to bypass the driver restriction. After the patch, the logs confirmed:

gpu:11090:11152 [1] NCCL INFO Channel 00/0 : 1[1] - 0[0] via P2P/direct pointer

Actual P2P Results

Once actual P2P communication was enabled, the gap between PCIe and NVLink vanished:

  • Prompt Processing: Virtually identical to NVLink.
  • FSDP Training: Achieved >90%>90\%>90% of the performance of the NVLink bridge.

🖥️ The Consumer Platform Dilemma

In my specific case, NVLink is largely redundant because I use a server-grade Epyc platform with abundant PCIe lanes. However, for the average consumer, the situation is different.

Most consumer motherboards lack true x16\text{x16}x16 scalability. Many claim to have two x16\text{x16}x16 slots, but they actually bifurcate the bandwidth into x8/x8\text{x8/x8}x8/x8 when both are populated.

High-End Consumer Board Comparison

MotherboardMarketed NameApprox. PriceActual PCIe Capability
MSI MEG X870EGODLIKE X EDITION$1,300x16\text{x16}x16 or x8/x8\text{x8/x8}x8/x8
Gigabyte Z890AORUS XTREME AI TOP1,000−1,000 - 1,000−1,800x16\text{x16}x16 or x8/x8\text{x8/x8}x8/x8
Asus ProArt B650Creator$230x16\text{x16}x16 or x8/x8\text{x8/x8}x8/x8

It is hilarious that boards branded as "EXTREME AI" or "GODLIKE" offer the same PCIe limitations as a budget-friendly ProArt board. In these scenarios, an NVLink bridge is highly valuable because it completely bypasses the PCIe bus, allowing GPUs to communicate at maximum speed regardless of the motherboard's lane limitations.

📉 Performance under PCIe Throttling

To simulate a consumer environment, I manually throttled my PCIe slots in the BIOS to x8\text{x8}x8 and x4\text{x4}x4.

Tensor Parallel Inference Results:

  • NVLink: Performance remained constant (unaffected by PCIe).
  • P2P (x8\text{x8}x8): ≈5%\approx 5\%≈5% performance drop.
  • P2P (x4\text{x4}x4): ≈15%\approx 15\%≈15% performance drop.
  • SHM: Significantly slower than both.

For FSDP Training, the degradation of P2P performance as PCIe lanes decreased was even more severe, making NVLink a much more attractive option for those on limited-lane platforms.