ao486: A Verilog-based x86 Core for the 486 SX (2014)

The ao486 is an open-source Verilog implementation of an x86-compatible processor, specifically designed to replicate the full feature set of the Intel 486 SX.

The development of this core relied heavily on the Bochs software emulator for modeling and verification. Beyond the CPU itself, the project provides a complete System-on-Chip (SoC) capable of booting legacy operating systems such as Microsoft Windows 95 and Linux kernel v3.13.

🏗️ System Architecture

The ao486 SoC integrates the processor with various legacy peripherals via Altera Qsys.

Processor Specifications

The core utilizes a pipeline architecture consisting of four primary stages:

decode
read
execute
write

Key Technical Features:

Instruction Set: Full 486 implementation, including the CPUID instruction.
Caching:
- Instruction Cache: $16\text{ kB}$
- Data Cache: $16\text{ kB}$ (Write-back)
Memory Management: A Translation Lookaside Buffer (TLB) with 32 entries.
Interconnect: Memory and I/O access are handled via Altera Avalon interfaces.

SoC Component Breakdown

Component	Description
Storage	IDE HDD and Floppy controller (both mapped to an HDL SD card driver).
Interrupts/DMA	8259 Programmable Interrupt Controller (PIC) and 8237 DMA controller.
Audio	Sound Blaster 2.0 with DSP and OPL2 (~~FM synthesis is fully functional~~ $\rightarrow$ partially working), outputting via a WM8731 codec.
Timers/IO	8254 PIT, 8042 Keyboard/Mouse controller, and a Real-Time Clock (RTC).
Video	Standard VGA implementation.
Management	An Altera NIOS2 processor handles system management and the On-Screen Display (OSD).

🛠️ Hardware Implementation & Resources

The project is targeted for the Terasic DE2-115 board, utilizing the Altera Cyclone IV E (EP4CE115F29C7) FPGA.

Resource Utilization Table

Unit	Logic Cells	M9K Memory Blocks
ao486 processor	36,517	47
Floppy	1,514	2
HDD	2,071	17
NIOS2	1,056	3
On-chip (NIOS2)	0	32
PC DMA	848	0
PIC	388	0
PIT	667	0
PS2	742	2
RTC	783	1
Sound	37,131	29
VGA	2,534	260

Fitter Report Summary (Quartus II 13.1.0)

Status: Successful (Mar 30, 2014)

Total Logic Elements: $91,256 / 114,480$ (80%)

Combinational Functions: $86,811 / 114,480$ (76%)

Dedicated Registers: $26,746 / 114,480$ (23%)

Memory Bits: $2,993,408 / 3,981,312$ (75%)

Embedded Multipliers: $44 / 532$ (8%)

PLLs: $1 / 4$ (25%)

Max Frequency: $39\text{ MHz}$

📈 Performance & Compatibility

CPU Benchmarks

Testing was performed using the DosTests.zip suite.

Benchmark	Optimization	Result (VAX MIPS)
Dhrystone 1	Non-Optimized	1.00
Dhrystone 1	Optimized	4.58
Dhrystone 2	Non-Optimized	1.01
Dhrystone 2	Optimized	3.84

Software Support

The ao486 has been verified to run the following:

MS-DOS 6.22
Windows for Workgroups 3.11
Windows 95
Linux 3.13.1

💾 BIOS and Firmware

The system utilizes a combination of open-source BIOS projects:

System BIOS: Based on Bochs version 2.6.2.
VGA BIOS: Based on VGABIOS version 0.7a.
- Note: VBE extensions are disabled as the VGA model does not support them.

⚖️ Licensing

Directory/File	License
`rtl`, `ao486_tool`, `sim`	BSD License
`bochs486`, `bochsDevs`	LGPL License
`sd/fd_1_44m/fdboot.img`	FreeDOS Project
`sd/bios/bochs_legacy`	Bochs Project (Compiled)
`sd/vgabios/vgabios-lgpl`	VGABIOS Project (Compiled)

🚀 Compilation Guide

Requirements

Altera Quartus II (Required for SoC and NIOS II synthesis).
Any standard Verilog compiler (for the standalone ao486 processor).

[!WARNING] Some synthesis project files may contain broken file paths in the current version.

Build Instructions

1. Processor & SoC

To build the CPU: Open syn/components/ao486/ao486.qpf.
To build the SoC: Open syn/soc/soc.qpf.
- Crucial: You must generate the Qsys system before starting the Quartus compilation.

2. BIOS Compilation

To build the system BIOS from source:

# Extract bochs-2.6.2, then in the source folder:
patch -p1 (path to bios/bochs-2.6.2 patch)
./configure
make
cd bios
make
# Result: BIOS-bochs-legacy

3. VGABIOS Compilation

To build the VGA BIOS from source:

# Extract vgabios-0.7a, then in the source folder:
patch -p1 (path to bios/vgabios-0.7a patch)
make
# Result: VGABIOS-lgpl-latest.bin

4. Deployment on DE2-115

Compile the SoC project via syn/soc/soc.qpf in Quartus II.
Use the Nios II Software Build Tools for Eclipse to compile the firmware.
Set your workspace to syn/soc/firmware.