🏛️ Assembly Hall of Shame

While most developers spend their time optimizing for speed racing to the top of performance benchmarks, the Assembly Hall of Shame pursues a different goal: finding the absolute floor of single-instruction execution time.

"Instruction latency analysis usually focuses on performance optimization—making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance."

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🏆 The Reigning Champion 🏆

The current record holder for the slowest x86 instruction is fxrstor64.

The Strategy: PCIe Fabric Starvation

The goal is to force the CPU to wait as long as possible. By using fxrstor64 to load a 512-byte state from a high-latency MMIO region within the PCIe fabric, the instruction is already slow. To make it worse, a "fleet" of other CPU cores is used to "hammer" a different high-latency MMIO register with tight 4-byte reads. This saturates the PCIe root complex and endpoint with non-posted transactions, forcing the original fxrstor64 load to queue behind a massive wall of contending traffic.

The Stats:

• Hardware: AMD Ryzen 7 5800H
• The "Slow" Instruction: fxrstor64 %rsi
• The "Hammer" Code:

  ; CPU 0 (The Victim)
  movl $0xfcc68830, %rsi
  fxrstor64 %rsi
  
  ; CPUs 1..N (The Hammers)
  movl 0xfcc68858, %eax
  

• Score: 198,002,498,236 cycles
• Wall Time: $\approx 62$ seconds

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🎖️ Honorable Mentions

A notable mention goes to a spec-violating unaligned ymm0 load. By forcing non-posted dword transactions from stalled GPU registers, this technique was used to undermine the design of System Management Mode (SMM) in the smiiiiiiiiiiiiiiii project: vmovdqu 0xfcc003b1, %ymm0

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📜 The Rules of Engagement

To keep the competition fair, the following constraints are applied:

• Single Instruction Scoring: Setup code is permitted, but only one specific instruction is timed.
• No Handler Timing: For instructions that are trapped, emulated, or virtualized, only the time to trigger the trap is measured (not the handler's execution).
• Stock Hardware: No physical modifications; all platforms must remain in factory configurations.

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📉 The Leaderboard (Intel Core i7-8559U @ 2.7GHz)

The following table summarizes the "race to the bottom" on a standard Intel chip.

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🔍 Deep Dive into Strategies

1. The Divider (idiv)

To maximize latency, the dividend is set to $2^{65}$ (using rdx:rax) with a small divisor (5). This pushes the quotient above the sign-extension ceiling, forcing the microcode to take the longest possible path. $\text{Quotient} = \frac{2^{65}}{5} \approx 7.4 \times 10^{18}$

2. The Stack Frame (enter)

By setting the nesting depth to the maximum of 31, the CPU is forced to perform 30 display-pointer loads and pushes.

enter $0, $31 ; 0 bytes allocated, depth 31

3. Floating Point Assists (fldl & fadd)

Using denormal (subnormal) numbers triggers a "microcode assist," which is significantly slower than the fast path.

• fldl: Load a small denormal.
• fadd: Use a subnormal source operand (e.g., $1 \times 10^{-310}$).

4. Memory Fencing (mfence)

The strategy here is to saturate all write-combining line-fill buffers (LFBs) using movnti stores to 16 different cache lines. The mfence instruction cannot retire until the entire LFB write path is drained to the uncore.

5. The Split Lock

The goal is to align a lock-prefixed operand so that it straddles a cache-line boundary. This forces the processor to assert an external bus lock rather than using the internal cache-locking mechanism.