Voyager 1 FDS Computer Emulator

This project provides a functional emulation of the Flight Data Subsystem (FDS) used aboard the Mariner Jupiter-Saturn '77 (Voyager) spacecraft.

🌌 Current Mission Status: Voyager 1

The probe is currently traversing the interstellar medium at a staggering distance:

Distance: $24,596,234,112 \text{ km}$
One-way Signal Latency: $\approx 22\text{h } 51\text{m}$

🛠️ Emulator Interface & Controls

The emulator allows users to interact with the FDS assembly through a virtual console.

Execution Controls: ▶ RUN | ⏭ STEP | ⟲ RESET

Available Demo Programs:

Countdown from 10
Add Two Numbers
Multiply (via Repeated Addition)
Memory Banking Demonstration

🖥️ System State

Register	Value	Description
`RA`	`0000`	Accumulator
`RB`	`0000`	Auxiliary Register
`PC`	`0000`	Program Counter
`Cycles`	`0`	Total clock cycles elapsed

Status Flags: ZERO | OVFL | CARRY | BANK

Memory View: 000: 0000 0000 0000 0000

⚙️ Technical Architecture

The FDS is a relic of 1970s engineering, possessing capabilities that are ~~blazing fast~~ glacial by today's computing standards.

Feature	Specification
Clock Speed	$806.4 \text{ kHz}$ ( $\approx 400,000 \text{ IPS}$ )
Cycle Time	$2.48 \text{ \mu s}$
Memory	$8\text{K} \times 16\text{-bit}$ CMOS RAM (Split into two $4\text{K}$ banks)
Registers	`RA`, `RB`, $128$ Working registers, and special-purpose registers
I/O	Serial: $32\text{-bit}$ input / $16\text{-bit}$ output
Interrupts	$2.5\text{ ms}$ periodic intervals for error recovery
Word Format	$16\text{-bit}$ total ( $12\text{-bit}$ address / $4\text{-bit}$ opcode)

Data Flow & DMA

The system utilizes 4 Direct Memory Access (DMA) channels operating at $115.2\text{ kbps}$ to handle instrument data.

📜 Instruction Set

The FDS utilizes a concise set of operations to manage spacecraft telemetry and commands.

; FDS Opcode Reference
MLD  ; Load memory value into RA
MRD  ; Store RA value into memory
ADD  ; RA = RA + memory
SUB  ; RA = RA - memory
AND  ; RA = RA & memory
JMP  ; Jump to address
SKZ  ; Skip next instruction if zero
SKP  ; Skip next instruction if positive
WAT  ; Halt execution
DW   ; Define word (data)

📚 Archival Sources

The emulator's logic is based on original JPL documentation spanning 1974-1977. These historical records have been meticulously preserved by the Wichita State University Special Collections.