A Switch-Level Simulation Model for Integrated Logic Circuits (1981)

Executive Summary

In the early 1980s, the design of Very Large Scale Integration (VLSI) circuits faced a critical bottleneck: the gap between transistor-level accuracy and gate-level speed. While SPICE provided high fidelity, it was computationally prohibitive for entire chips. Conversely, logic simulators ignored electrical nuances like tri-state buffers and bus contention.

This paper proposes a Switch-Level Simulation Model that treats transistors as ideal switches, providing a pragmatic middle ground. By abstracting the physics while retaining the topology, designers can simulate complex integrated circuits with significantly reduced CPU overhead.

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1. The Theoretical Framework

The core philosophy is to replace the complex differential equations of MOSFETs with a simplified switching function. Instead of calculating precise currents, the model evaluates the connectivity of nodes.

1.1 Logic Value Definitions

To capture the behavior of integrated circuits, a standard binary system is insufficient. The model employs a four-value logic system:

Note: The X state is critical for detecting design flaws where two drivers attempt to force a node to opposite polarities simultaneously.

1.2 The Switch Abstraction

A transistor is modeled as a switch that is either Closed (conducting) or Open (non-conducting).

• NMOS Switch: Closes when the gate is 1.
• PMOS Switch: Closes when the gate is 0.

The electrical behavior at a node $n$ can be represented by the summation of influences: $V_n = \frac{\sum (G_i \cdot V_i)}{\sum G_i}$ Where $G_i$ represents the conductance of the $i$-th switch. In this simplified model, we assume $G$ is either $\infty$ (closed) or $0$ (open).

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2. Simulation Methodology

The simulation follows an event-driven architecture. When an input changes, the model updates the state of all connected switches and re-evaluates the affected nodes.

2.1 The Evaluation Algorithm

The process can be visualized as a recursive update cycle:

2.2 Handling Contention and Strength

To refine the model, the paper introduces the concept of driver strength. Not all switches are equal; some are "stronger" (lower resistance) than others.

• Strong Driver: Overrides a weak driver.
• Weak Driver: Used for pull-up/pull-down resistors.

Purely binary logic cannot handle these cases, but the switch-level model resolves them by prioritizing the strongest connected path to $V_{DD}$ or $V_{SS}$.

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3. Implementation Details

The model is implemented using a directed graph where edges represent switches and vertices represent nodes.

3.1 Pseudo-Code for Node Evaluation

void evaluateNode(Node n) {
    bool connectedToVdd = false;
    bool connectedToVss = false;

    for (Switch s : n.connectedSwitches) {
        if (s.isOpen() == false) {
            if (s.getOtherEnd() == VDD) connectedToVdd = true;
            if (s.getOtherEnd() == VSS) connectedToVss = true;
        }
    }

    if (connectedToVdd && connectedToVss) n.value = 'X';
    else if (connectedToVdd) n.value = '1';
    else if (connectedToVss) n.value = '0';
    else n.value = 'Z';
}

3.2 Performance Metrics

The efficiency gain is staggering when compared to transistor-level models:

1. Memory Usage: Reduced by $\approx 10\times$ due to the elimination of complex device parameters.
2. Execution Speed: Increased by $100\times$ to $1000\times$ because the solver handles algebraic connectivity rather than differential equations.

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4. Verification Checklist

To ensure the simulation accurately reflects the physical hardware, the following tasks must be completed:

• Validate logic transitions for basic CMOS gates (NAND, NOR).
• Verify tri-state buffer isolation (Z-state).
• Test bus contention scenarios (X-state).
• Implement propagation delay $\Delta t$ based on RC constants.
• Integrate with higher-level architectural simulators.

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5. Conclusion

The proposed switch-level model provides a robust framework for the verification of integrated circuits. By sacrificing the granular precision of $\text{current } (I)$ and $\text{voltage } (V)$ curves, it gains the ability to simulate entire systems. This approach ensures that manual schematic checking is replaced by automated, reliable software verification, significantly shortening the design cycle for VLSI systems.

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Reference: A Switch-Level Simulation Model for Integrated Logic Circuits (1981). [pdf]