On Binary Translation and Its Consequences

By Chester Lam | Chips and Cheese

Entering the PC processor market is a daunting task for any chip designer. The consumer base is demanding, expecting not only raw speed across diverse software but also a level of flexibility that extends far beyond a curated limited set of approved applications.

A prime example of this challenge was the Microsoft Surface RT, which failed spectacularly over a decade ago. The reason? It couldn't execute the legacy programs that Windows users consider essential.

While modern 64-bit Arm cores—such as those from Qualcomm—now possess the raw horsepower to meet performance expectations, the "software wall" remains.

The Compatibility Hurdle

Transitioning the ecosystem to native aarch64 (64-bit Arm) is a grueling process:

• Developer Inertia: Getting software houses to port their apps to aarch64 is a slow crawl.
• Abandoned Software: Some critical tools will never be ported because they are no longer maintained and only exist as binary files.

Consequently, the success of Arm in the PC space depends on Microsoft's ability to make x86-64 binaries run flawlessly on aarch64 hardware. This is where Prism, the latest binary translator in Windows 11, comes into play.

The Mechanics of Prism

Prism functions by converting x86-64 instructions into aarch64 equivalents on the fly. This is an immense engineering challenge because:

1. Instruction sets don't always map 1:1.
2. The process must be incredibly fast to prevent sluggish app launches.
3. CPU overhead must be minimized to preserve battery and performance.

Inevitably, this process introduces a "translation tax." To quantify this, I utilized Geekbench 7, comparing the native aarch64 version against the x86-64 version running under Prism.

Note: While a single benchmark isn't a universal proxy for all software, it serves as a vital baseline for understanding architectural overhead.

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Experimental Setup

I utilized a variety of hardware to test these dynamics:

Testing Parameters:

• Iterations: 200 per workload (to ensure the data reflects the workload, not the test harness).
• Scale: Each workload executes roughly several trillion instructions.

Workload Characteristics

Geekbench 7 focuses on compute-bound tasks with high Instructions Per Cycle (IPC). Using Intel's Software Development Emulator (SDE) to mimic a Haswell CPU, I found that:

• Over 50% of workloads utilize AVX.
• Vector widths of 256-bit are common.

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The "Instruction Inflation" Effect

When comparing native execution to translated execution, the difference in instruction counts is staggering.

As a general rule of thumb, the number of instructions executed under translation follows this approximate ratio:

$I_{translated} \approx 2 \times I_{native}$

Except for the PDF Viewer workload, almost every test showed a massive inflation in the number of retired instructions. Interestingly, while Qualcomm cores reported higher retired counts than Neoverse N1/N2 (suggesting some hardware monitoring inaccuracies), the trend remained consistent across the board.

Hardware-Specific Tuning

Microsoft has indicated that Prism is not "one size fits all." It is specifically tuned for Qualcomm Snapdragon processors.

• General Support: Available for all Windows 11 24H2 Arm devices.
• Optimized Path: Leverages specific hardware features in the Snapdragon X series.
• Memory Ordering: Potentially leverages non-ISA guarantees (like store ordering) to improve efficiency.

Despite these optimizations, the instruction count remains similar across different cores (e.g., Ampere Altra's Neoverse N1 vs. Snapdragon), meaning the "inflation" is a result of the translation logic itself, not the target hardware.

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Performance Consequences

The "translation tax" is heavy. Every tested core suffered a performance drop equivalent to several hardware generations. However, the Snapdragon X2 Elite mitigates this through sheer brute force.

The X2 Elite features:

1. A 6-core "performance" cluster.
2. Two 6-core "prime" clusters (which I will refer to as E-Cores for simplicity).

Because these cores are significantly wider and clock higher than the Neoverse N1, the Snapdragon E-Cores actually outperform the native Neoverse N1, even while paying the Prism translation penalty.

Summary of Findings

• Translation Penalty: Severe across all architectures.
• Mitigation: High baseline IPC and clock speeds can mask the overhead.
• Efficiency: It remains unclear if Qualcomm's slightly lower penalty is due to Prism's specific optimizations or simply higher raw throughput.

The process of binary translation is a bit like using an LLM to rewrite code; the output gets the job done, but the "verbosity" (instruction count) increases significantly.

Additional Visuals from the Analysis: