Book Review: Is Parallel Programming Hard, and, if so, what can you do about it?

Date: September 21, 2026
Reviewer: Andrew Helwer

I recently spent a significant amount of time diving into the free online textbook Is Parallel Programming Hard, And, If So, What Can You Do About It? written by the creator of the Linux kernel's RCU synchronization mechanism, Herwig McKenna (referred to as McKenney in some contexts). I've read enough to feel satiated for now, so I wanted to document my impressions while the details are still vivid.

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🌲 The Setting

This section is essentially the "tedious personal backstory" often found on food blogs; feel free to skip it if you just want the critique.

For the last decade, my career has been centered on TLA+ and distributed systems. However, I felt a need for a pivot. In 2022, I attempted to transition into Lean with the goal of securing a highly specific, perhaps non-existent, role: formalizing quantum information processing results for researchers. I succeeded in this I eventually burned out on that pursuit, though in hindsight—given the explosion of automated theorem proving—my instincts may have been saving me from a dead end.

This led me to the 2026 Software Should Work conference in Columbia, Missouri. While the event was excellent, the highlight was Filip Pizlo's presentation on Fil-C. Through conversations with Fil about interpreters and concurrency, I had a humbling realization: despite my TLA+ experience, I knew very little about actual concurrency.

Key Realizations from Fil:

• Writing a lock-free garbage collector is incredibly difficult.
• TLA+ may lack the ergonomics required to reason about events happening literally simultaneously on a multicore CPU.
• The critical importance of analyzing concurrent algorithms for linearizability.

To bridge this gap, I sought a resource focusing on lock-free techniques and CPU cache effects rather than standard mutexes or message-passing. This textbook seemed ideal, especially given its presence in several Hacker News threads (dating back to 2011, 2014, 2015, 2020, 2021, and 2023). I decided to stop over-analyzing the choice procrastinating and just start reading.

The Environment

I read the text during a 10-day family visit to a secluded, wooded area of Canada. The conditions were as follows:

• Quiet, natural surroundings.
• A cool, screened-in porch.
• High-speed internet via satellite/cell towers.
• A nightmare of a mosquito season.

The insects acted as "guards," ensuring I stayed inside the screen and focused on my studies.

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🛠️ The Textbook Format

The book is available in three PDF variations. I used a Pine64 PineNote for my reading.

The User Experience (UX)

The book utilizes links for two main purposes:

1. Knowledge Checks: Quick questions that link directly to their answers.
2. References: Citations and footnotes.

Unfortunately, the sheer volume of footnotes is overwhelming. If you are using an e-reader without physical buttons, the experience is frustrating. I frequently accidentally triggered a link while trying to turn the page, teleporting me to a random section of the book. This made flipping between sections nearly impossible. Furthermore, some links are placed so closely together that a touch screen cannot distinguish between them.

# The Reader's Dilemma
if disable_links == True:
    navigation_is_smooth = True
    knowledge_checks_accessible = False
else:
    navigation_is_smooth = False
    knowledge_checks_accessible = True

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📖 Content Analysis: The Basics

For my specific knowledge level, the presentation was nearly perfect. The book eases in with introductory chapters before accelerating in Chapter 3: Hardware and its Habits.

This chapter explores the high-level mechanics of modern CPUs—specifically what optimizes performance and what hinders it. I found Section 3.2.1 (Hardware System Architecture) particularly gripping, as it details the process of a CPU core writing to a memory address not currently in its cache.

The "Missing" Piece

While the book is thorough, I felt there was a missed opportunity regarding the MESI protocol. My intuition regarding how caches mediate concurrent reads and writes was non-existent, and I had to search externally to understand the concepts in Section 3.2.1.

The MESI protocol is only mentioned in the appendix, but I believe it belongs in the main text. Understanding it significantly improved my comprehension of the rest of the material.

Conceptual Summary

The relationship between memory and cache can be thought of as a mapping function: $\text{Memory Address} \rightarrow \text{Cache Line} \rightarrow \text{CPU Core}$